? semiconductor components industries, llc, 2011 december, 2011 ? rev. 8 1 publication order number: ngd18n40clb/d ngd18n40clb, ngd18n40aclb ignition igbt, 18 a, 400 v n ? channel dpak this logic level insulated gate bipolar transistor (igbt) features monolithic circuitry integrating esd and over ? voltage clamped protection for use in inductive coil drivers applications. primary uses include ignition, direct fuel injection, or wherever high voltage and high current switching is required. features ? ideal for coil ? on ? plug applications ? dpak package offers smaller footprint for increased board space ? gate ? emitter esd protection ? temperature compensated gate ? collector voltage clamp limits stress applied to load ? integrated esd diode protection ? new design increases unclamped inductive switching (uis) energy per area ? low threshold voltage interfaces power loads to logic or microprocessor devices ? low saturation voltage ? high pulsed current capability ? optional gate resistor (r g ) and gate ? emitter resistor (r ge ) ? emitter ballasting for short ? circuit capability ? these are pb ? free devices maximum ratings (t j = 25 c unless otherwise noted) rating symbol value unit collector ? emitter voltage v ces 430 v dc collector ? gate voltage v cer 430 v dc gate ? emitter voltage v ge 18 v dc collector current ? continuous @ t c = 25 c ? pulsed i c 15 50 a dc a ac esd (human body model) r = 1500 , c = 100 pf esd 8.0 kv esd (machine model) r = 0 , c = 200 pf esd 800 v total power dissipation @ t c = 25 c derate above 25 c p d 115 0.77 watts w/ c operating and storage temperature range t j , t stg ? 55 to +175 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. 18 amps, 400 volts v ce(on) 2.0 v @ i c = 10 a, v ge 4.5 v dpak case 369c style 7 1 2 3 4 http://onsemi.com marking diagram 1 gate 4 collector 2 collector 3 emitter yww g18 n40xg g18n40x = device code x = b or a y = year ww = work week g = pb ? free device device package shipping ? ordering information NGD18N40CLBT4G dpak (pb ? free) 2500/tape & reel ngd18n40aclbt4g dpak (pb ? free) 2500/tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. c e g r g r ge
ngd18n40clb, ngd18n40aclb http://onsemi.com 2 unclamped collector ? to ? emitter avalanche characteristics ( ? 55 t j 175 c) characteristic symbol value unit single pulse collector ? to ? emitter avalanche energy v cc = 50 v, v ge = 5.0 v, pk i l = 21.1 a, l = 1.8 mh, starting t j = 25 c v cc = 50 v, v ge = 5.0 v, pk i l = 16.2 a, l = 3.0 mh, starting t j = 25 c v cc = 50 v, v ge = 5.0 v, pk i l = 18.3 a, l = 1.8 mh, starting t j = 125 c e as 400 400 300 mj reverse avalanche energy v cc = 100 v, v ge = 20 v, pk i l = 25.8 a, l = 6.0 mh, starting t j = 25 c e as(r) 2000 mj maximum short ? circuit times ( ? 55 c t j 150 c) short circuit withstand time 1 (see figure 17, 3 pulses with 10 ms period) t sc1 750 s short circuit withstand time 2 (see figure 18, 3 pulses with 10 ms period) t sc2 5.0 ms thermal characteristics thermal resistance, junction to case r jc 1.3 c/w thermal resistance, junction to ambient dpak (note 1) r ja 95 c/w maximum lead temperature for soldering purposes, 1/8 from case for 5 seconds t l 275 c electrical characteristics characteristic symbol test conditions temperature min typ max unit off characteristics collector ? emitter clamp voltage bv ces i c = 2.0 ma t j = ? 40 c to 150 c 380 395 420 v dc i c = 10 ma t j = ? 40 c to 150 c 390 405 430 zero gate voltage collector current i ces v ce = 350 v, v ge = 0 v t j = 25 c ? 2.0 20 a dc t j = 150 c ? 10 40* t j = ? 40 c ? 1.0 10 v ce = 15 v, v ge = 0 v t j = 25 c ? ? 2.0 reverse collector ? emitter leakage current i ecs v ce = ? 24 v t j = 25 c ? 0.7 1.0 ma t j = 150 c ? 12 25* t j = ? 40 c ? 0.1 1.0 reverse collector ? emitter clamp voltage b vces(r) i c = ? 75 ma t j = 25 c 27 33 37 v dc t j = 150 c 30 36 40 t j = ? 40 c 25 32 35 gate ? emitter clamp voltage bv ges i g = 5.0 ma t j = ? 40 c to 150 c 11 13 15 v dc gate ? emitter leakage current i ges v ge = 10 v t j = ? 40 c to 150 c 384 640 700 a dc gate resistor r g ? t j = ? 40 c to 150 c ? 70 ? gate emitter resistor r ge ? t j = ? 40 c to 150 c 10 16 26 k 1. when surface mounted to an fr4 board using the minimum recommended pad size. *maximum value of characteristic across temperature range.
ngd18n40clb, ngd18n40aclb http://onsemi.com 3 electrical characteristics (continued) characteristic symbol test conditions temperature min typ max unit on characteristics (note 2) gate threshold voltage v ge(th) i c = 1.0 ma, v ge = v ce t j = 25 c 1.1 1.4 1.9 v dc t j = 150 c 0.75 1.0 1.4 t j = ? 40 c 1.2 1.6 2.1* threshold temperature coefficient (negative) ? ? ? ? 3.4 ? mv/ c collector ? to ? emitter on ? voltage v ce(on) i c = 6.0 a, v ge = 4.0 v t j = 25 c 1.0 1.4 1.6 v dc t j = 150 c 0.9 1.3 1.6 t j = ? 40 c 1.1 1.45 1.7* i c = 8.0 a, v ge = 4.0 v t j = 25 c 1.3 1.6 1.9* t j = 150 c 1.2 1.55 1.8 t j = ? 40 c 1.4 1.6 1.9* i c = 10 a, v ge = 4.0 v t j = 25 c 1.4 1.8 2.05 t j = 150 c 1.4 1.8 2.0 t j = ? 40 c 1.4 1.8 2.1* i c = 15 a, v ge = 4.0 v t j = 25 c 1.8 2.2 2.5 t j = 150 c 2.0 2.4 2.6* t j = ? 40 c 1.7 2.1 2.5 i c = 10 a, v ge = 4.5 v t j = 25 c 1.3 1.8 2.0* t j = 150 c 1.3 1.75 2.0* t j = ? 40 c 1.4 1.8 2.0* i c = 6.5 a, v ge = 3.7 v t j = 25 c ? ? 1.65 forward transconductance gfs v ce = 5.0 v, i c = 6.0 a t j = ? 40 c to 150 c 8.0 14 25 mhos dynamic characteristics input capacitance c iss v cc = 25 v, v ge = 0 v f = 1.0 mhz t j = ? 40 c to 150 c 400 800 1000 pf output capacitance c oss 50 75 100 transfer capacitance c rss 4.0 7.0 10 switching characteristics turn ? off delay time (resistive) t d(off) v cc = 300 v, i c = 6.5 a r g = 1.0 k , r l = 46 , t j = 25 c ? 4.0 10 sec fall time (resistive) t f v cc = 300 v, i c = 6.5 a r g = 1.0 k , r l = 46 , t j = 25 c ? 9.0 15 turn ? on delay time t d(on) v cc = 10 v, i c = 6.5 a r g = 1.0 k , r l = 1.5 t j = 25 c ? 0.7 4.0 sec rise time t r v cc = 10 v, i c = 6.5 a r g = 1.0 k , r l = 1.5 t j = 25 c ? 4.5 7.0 2. pulse test: pulse width 300 s, duty cycle 2%. *maximum value of characteristic across temperature range.
ngd18n40clb, ngd18n40aclb http://onsemi.com 4 typical electrical characteristics (unless otherwise noted) 5 v gate ? to ? emitter voltage (volts) 0 40 6 10 4 2 i c, collector current (amps) 0 60 20 30 50 8 1357 0 40 6 10 4 2 i c, collector current (amps) 0 v ce , collector to emitter voltage (volts) figure 1. output characteristics figure 2. output characteristics 0 25 20 15 10 2 1 5 60 0 4 35 figure 3. output characteristics v ge , gate to emitter voltage (volts) figure 4. transfer characteristics i c, collector current (amps) figure 5. collector ? to ? emitter saturation voltage versus junction temperature figure 6. collector ? to ? emitter voltage versus gate ? to ? emitter voltage 60 v ge = 10 v v ce , collector to emitter voltage (volts) 20 30 50 8 1357 5 v t j = 25 c t j = ? 40 c v ge = 10 v 4.5 v 4 v 3.5 v 3 v 2.5 v t j = 150 c 678 4.5 v 4 v 3.5 v 3 v 2.5 v 0 40 6 10 4 2 i c, collector current (amps) 0 60 20 30 50 8 1357 v ce , collector to emitter voltage (volts) t j = 150 c v ge = 10 v 5 v 4.5 v 4 v 3.5 v 3 v 2.5 v 2.5 t j , junction temperature ( c) v ce , collector to emitter voltage (volts) ? 50 50 75 25 0 100 ? 25 125 1.0 3.0 0.5 2.0 0.0 3.5 4.0 1.5 150 v ge = 5 v i c = 25 a i c = 20 a i c = 15 a i c = 10 a i c = 5 a 2.5 collector to emitter voltage (volts) 367 58 49 1 0.5 2 0 3 1.5 10 i c = 15 a i c = 10 a i c = 5 a v ce = 10 v t j = 25 c t j = ? 40 c t j = 25 c 45 40 35 30 55 50
ngd18n40clb, ngd18n40aclb http://onsemi.com 5 v th ? 4 temperature ( c) gate threshold voltage (volts) ? 50 50 70 10 ? 10 90 ? 30 130 150 v th + 4 v th gate to emitter voltage (volts) 1.2 0.2 0 2 0.6 1 1.6 10000 1000 100 10 0 6 4 0 8 10 12 figure 7. collector ? to ? emitter voltage versus gate ? to ? emitter voltage figure 8. capacitance variation figure 9. gate threshold voltage versus temperature figure 10. minimum open secondary latch current versus temperature temperature ( c) i l , latch current (amps) figure 11. typical open secondary latch current versus temperature v ce , collector to emitter voltage (volts) figure 12. inductive switching fall time versus temperature temperature ( c) c, capacitance (pf) switching time ( s) 0 120 60 40 20 140 180 ? 50 50 75 25 0 100 ? 25 125 10 20 5 15 0 25 30 t j = 150 c 175 v cc = 50 v v ge = 5.0 v r g = 1000 l = 6 mh 200 80 100 160 ? 50 50 70 30 ? 10 90 ? 30 130 150 t f v cc = 300 v v ge = 5.0 v r g = 1000 i c = 10 a l = 300 h c rss c iss c oss 2.5 367 58 49 1 0.5 2 0 3 1.5 10 i c = 15 a i c = 10 a i c = 5 a collector to emitter voltage (volts) 1 30 110 0.4 0.8 1.4 1.8 150 l = 3 mh l = 1.8 mh temperature ( c) i l , latch current (amps) ? 50 50 75 25 0 100 ? 25 125 10 20 5 15 0 25 30 175 v cc = 50 v v ge = 5.0 v r g = 1000 l = 6 mh 150 l = 3 mh l = 1.8 mh 2 10 110 t d(off)
ngd18n40clb, ngd18n40aclb http://onsemi.com 6 100 10 0.1 1 0.01 figure 13. single pulse safe operating area (mounted on an infinite heatsink at t a = 25 c) collector ? emitter voltage (volts) figure 14. single pulse safe operating area (mounted on an infinite heatsink at t a = 125 c) collector ? emitter voltage (volts) collector current (amps) collector current (amps) 1 100 10 1000 100 10 0.1 1 0.01 1 100 10 1000 100 s 10 ms 1 ms 100 ms dc 100 s 10 ms 1 ms 100 ms dc 100 10 0.1 1 0.01 collector ? emitter voltage (volts) collector ? emitter voltage (volts) collector current (amps) collector current (amps) 1 100 10 1000 100 10 0.1 1 0.01 1 100 10 1000 t 1 = 1 ms, d = 0.05 t 1 = 2 ms, d = 0.10 t 1 = 3 ms, d = 0.30 t 1 = 1 ms, d = 0.05 t 1 = 2 ms, d = 0.10 t 1 = 3 ms, d = 0.30 figure 15. pulse train safe operating area (mounted on an infinite heatsink at t c = 25 c) figure 16. pulse train safe operating area (mounted on an infinite heatsink at t c = 125 c) 5.0 v v in r g = 1 k l = 10 h r l = 0.1 v batt = 16 v figure 17. circuit configuration for short circuit test #1 figure 18. circuit configuration for short circuit test #2 5.0 v v in r g = 1 k l = 10 h r l = 0.1 v batt = 16 v r s = 55 m
ngd18n40clb, ngd18n40aclb http://onsemi.com 7 0.2 0.00001 0.001 0.0001 0.1 100 0.1 0.0001 0.01 t,time (s) r(t), transient thermal resistance ( c/watt) single pulse 1 0.1 0.05 0.02 0.01 duty cycle = 0.5 0.01 figure 19. transient thermal resistance (non ? normalized junction ? to ? ambient mounted on minimum pad area) 1 10 0.001 p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 d curves apply for power pulse train shown read time at t 1 t j(pk) ? t a = p (pk) r ja (t) r jc r(t) for t 0.2 s
ngd18n40clb, ngd18n40aclb http://onsemi.com 8 package dimensions style 7: pin 1. gate 2. collector 3. emitter 4. collector dpak case 369c issue d b d e b3 l3 l4 b2 e m 0.005 (0.13) c c2 a c c z dim min max min max millimeters inches d 0.235 0.245 5.97 6.22 e 0.250 0.265 6.35 6.73 a 0.086 0.094 2.18 2.38 b 0.025 0.035 0.63 0.89 c2 0.018 0.024 0.46 0.61 b2 0.030 0.045 0.76 1.14 c 0.018 0.024 0.46 0.61 e 0.090 bsc 2.29 bsc b3 0.180 0.215 4.57 5.46 l4 ??? 0.040 ??? 1.01 l 0.055 0.070 1.40 1.78 l3 0.035 0.050 0.89 1.27 z 0.155 ??? 3.93 ??? notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inches. 3. thermal pad contour optional within di- mensions b3, l3 and z. 4. dimensions d and e do not include mold flash, protrusions, or burrs. mold flash, protrusions, or gate burrs shall not exceed 0.006 inches per side. 5. dimensions d and e are determined at the outermost extremes of the plastic body. 6. datums a and b are determined at datum plane h. 12 3 4 5.80 0.228 2.58 0.102 1.60 0.063 6.20 0.244 3.00 0.118 6.17 0.243 mm inches scale 3:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* h 0.370 0.410 9.40 10.41 a1 0.000 0.005 0.00 0.13 l1 0.108 ref 2.74 ref l2 0.020 bsc 0.51 bsc a1 h detail a seating plane a b c l1 l h l2 gauge plane detail a rotated 90 cw on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. ngd18n40clb/d publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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